The present invention refers to a circuit system to codify NRZ type binary signals into CMI type binary signals.
In the transmission of data having electric cables as physical support, binary codification systems are used which permit the transmission of electric signals such as the clock signal, also called synchronism signals, and the data signal.
Binary codes consist of zeros and ones and in the base band transmission one of the possible codes is the so-called NRZ (Nonreturn to zero), that is a code in which there is no return to a fixed value like zero in the interval of a bit. This means that a signal in base band has a constant level in the interval of a bit and the levels to represent a bit are two so that each level corresponds to one logic state of the data, that is xe2x80x9c1xe2x80x9d bit (called Mark) corresponds to a high value and xe2x80x9c0xe2x80x9d bit (called Space) corresponds to a low value.
The NRZ code has two big disadvantages when it is transmitted on a line: 1) the presence of a long string of xe2x80x9c0xe2x80x9d prevents the clock signal from being extracted; 2) the presence of transformers at the extremities of the line, called repeaters, and the eventual intermediate amplifiers do not let the continuous component pass and therefore a succession of xe2x80x9c1xe2x80x9d bits is transformed into a succession of xe2x80x9c0xe2x80x9d bits.
To overcome the first disadvantage a solution has been adopted, which is called ADI (Alternate Digit Inversion), in which only the even bits are systematically inverted.
To overcome the second disadvantage the binary code ADI is converted into a code called AMI (Alternate Mark Inversion) in which the xe2x80x9c0xe2x80x9d bit is represented by a low level for the entire duration of the bit and the xe2x80x9c1xe2x80x9d bit is represented by a positive value or by a negative value alternately.
Nevertheless this last type of code also has the disadvantage that the presence of a long string of xe2x80x9c0xe2x80x9d prevents the clock signal from being extracted.
To eliminate these disadvantages the CMI code (Coded Mark Inversion) has been introduced, in which the xe2x80x9c0xe2x80x9d bit is codified so that for half the period there is a negative value and for the rest of the period there is a positive value, while the xe2x80x9c1xe2x80x9d bit is codified at a positive or negative value for the entire duration of the bit having inverse polarity to that used for the transmission of the last xe2x80x9c1xe2x80x9d bit.
To use the CMI code performance is requested for the transmission, with the STM-1e standard and 140 Mbps (Mega bounds per second), inside SDH (Synchronous Digital Hierarchy) type transmissions, set by ITU (International Telecom Unit) through G703, extremely strict for the waveforms of the voltage signal in time (Ref.: Physical/Electrical characteristics of Hierarchical Digital Interfaces G703 Recommendation, ed. November 1994, International Telecom Unit ITU-T).
The known circuit solutions provide that the input data are generated by an NRZ type source at a determined speed and with a determined clock signal and that said data are transformed in a CMI type code, that is a direct dependency of the final code with the input string of bits.
It results thus, that said circuit solutions can not fail the compliance with the performances but are not capable of making well defined transitions respecting the time masks set by ITU through G703 because the physical path taken by a xe2x80x9c1xe2x80x9d bit and by a xe2x80x9c0xe2x80x9d bit is different and this entails a different circuit reply with the introduction of various delays, phase displacements and distinct attenuation for the bits.
In view of the state of the art described, object of the present invention is to prevent the circuit paths followed by the bits through the various decoding phases from being different for the xe2x80x9c1xe2x80x9d bit and for the xe2x80x9c0xe2x80x9d bit, that is that the definition of the transition depends on the codified bit string.
According to the present invention, this object is reached through a circuit system suitable for codifying NRZ type binary signals into CMI type binary signals, characterized by a presynchronization device which receives in input said NRZ type binary signals and a clock signal out of phase, a first bistable means that receives a synchronous clock signal and the output of said presynchronization device, a combinatory logical device that receives said NRZ type binary signals and the output of said first bistable means, a second bistable means that receives said synchronous clock signal and the output of said combinatory logical device, a third bistable means that receives said synchronous clock signal and the output of said presynchronization device, an EXOR type logical gate that receives the outputs of said second and third bistable means and generates an output that is the input of said combinatory logical device so as to determine an identical physical path for the codification of the xe2x80x9c1xe2x80x9d bit and the xe2x80x9c0xe2x80x9d bit, whether the transition is on the leading and/or trailing edges or at mid period, bits present in said NRZ type binary signals, so that the parameters set by the G703 ITU standard for the creation of said CMI type binary signals are observed.
Thanks to the present invention a code can be made both for the xe2x80x9c1xe2x80x9d bit and for the xe2x80x9c0xe2x80x9d bit through an identical circuit that makes the same path so that the CMI code is implemented, so as to observe the specifications set by ITU through G703, thus avoiding all the disymmetries produced by the known art.